This application claims benefit of priority under 35 USC xc2xa7119 to Japanese patent application No.2000-160506, filed on May 30, 2000, the contents of which are incorporated by reference herein.
1. Field of the Invention
The present invention relates generally to a semiconductor pattern defect inspection. More specifically, the invention relates to a simulated defective wafer and a pattern defect inspection recipe preparing method for use in a semiconductor pattern defect inspection.
2. Description of the Prior Art
Referring to the flow chart of FIG. 14, an example of a conventional pattern defect inspection recipe preparing method will be described below.
First, a wafer serving as an object to be inspected is prepared (step S91). Then, tentative parameters for recipe are selected (step S92) to prepare a provisional inspection recipe (step S93). Then, the wafer serving as the object to be inspected is actually inspected to observe a detected defect (step S94). On the basis of the kind of the defect (which will be hereinafter referred to as a xe2x80x9cdefect kindxe2x80x9d) and the size of the defect, it is determined whether a defect detection sensitivity based on the provisional inspection recipe reaches a desired detection sensitivity (step S95). If it is not determined that the defect detection sensitivity reaches the desired detection sensitivity, a series of procedures including the selection of recipe parameters, the preparation of a provisional inspection recipe, the inspection of the wafer and the observation of defects are repeated (steps S92 through S95). If it is determined that the defect detection sensitivity reaches the desired detection sensitivity, finally selected recipe parameters are decided as recipe parameters suitable for inspection (step S96), and the provisional inspection recipe at that time is registered with a defect inspection system as a defect inspection recipe (step S97) to end the preparation of the inspection recipe.
However, in the above described conventional inspection recipe preparing method, there are the following problems.
That is, since the wafer serving as an object to be inspected is an actual semiconductor product or TEG (Test Element Group), it is not possible to previously obtain defect information on what kinds of defects and how many defects actually exist. Therefore, it is not possible to determine whether all of defect kinds to be detected have actually been detected, namely, whether other defect kinds can not be detected or no pattern defect exists. In addition, there is also a problem in that the quality of an inspection recipe is influenced by the level of skill of a person who prepares the inspection recipe.
Furthermore, when a simulated defect wafer, not an actual wafer, is intended to be used, a conventional simulated defect wafer in a monolayer structure is only prepared. For that reason, it is only possible to prepare a defect kind of a flat layer as simulated defects 101 and 102 shown in FIG. 15. However, as shown in FIG. 16, many actual defects are formed at various positions in vertical directions (in directions perpendicular to the surface of the substrate), such as a defect 103 formed on a patterned layer and a defect 104 formed in a gap between patterned layers on a substrate. It is difficult to realize such defects by a simulated defect wafer in a monolayer structure.
It is therefore a first object of the present invention to provide a simulated defective wafer for a defect inspection in view of various defect kinds.
It is a second object of the present invention to provide an inspection recipe preparing method capable of detecting a desired defect kind without omission independent of the level of skill of a person who prepares an inspection recipe.
According to a first aspect of the present invention, there is provided a simulated defective wafer comprising: a simulated normal layer which is formed on a semiconductor substrate so that the height of the top face of the simulated normal layer from the surface of the semiconductor substrate is a first height; and a first simulated defect layer which is formed on the semiconductor substrate so that the height of the top face of the first simulated defect layer from the surface of the semiconductor substrate is a second height which is different from the first height.
Since the first simulated defect layer is formed so that the height of the top face thereof is the second height which is different from the first height of the top face of the simulated normal layer from the surface of a semiconductor substrate, there is provided a simulated defective wafer capable of simulatively realizing defect layers, which are arranged at different positions in vertical directions, among actually possible defect layers. The simulated normal layer means a patterned layer wherein a pattern which is finely formed according to its design on a semiconductor wafer serving as an object to be inspected is simulatively formed on the simulated defective wafer.
The simulated defective wafer may preferably further comprise a second simulated defect layer which is formed on the semiconductor substrate so as to have a different plane shape from that of the simulated normal layer. By the second simulated defect layer, it is also possible to realize a defect kind in a plane shape.
The first simulated defect layer may preferably include a layer formed on the simulated normal layer. There is thus provided a simulated defective wafer wherein a typical defect kind which can appear on a wafer serving as an object to be inspected is simulatively realized.
In addition, the simulated normal layer, the first simulated defect layer and the second simulated defect layer may be constituted in a stacked layer which includes a conductive film respectively. Thus, there is provided a simulated defective wafer wherein a simulated defect is formed with an interconnection.
According to a second aspect of the invention, there is provided a method for preparing a defect inspection recipe for use in a semiconductor defect inspection system, the method comprising: a parameter setting step of setting a tentative recipe parameter; a first provisional recipe preparing step of preparing a first provisional defect inspection recipe on the basis of the recipe parameter; a simulated defect detecting step of detecting a defect of a simulated defective wafer using the first provisional pattern defect inspection recipe, a simulated defect data of the simulated defective wafer having previously been obtained, the simulated defect data being a data on a defect kind; a defect detection ratio calculating step of calculating a defect detection ratio of the first provisional pattern defect inspection recipe by comparing the detected defect data with the simulated defect data; a defect detection sensitivity determining step of determining a pattern defect detection sensitivity of the first provisional pattern defect inspection recipe by comparing the calculated pattern defect detection ratio with a desired pattern defect detection ratio; a first provisional recipe modifying step of repeating the first provisional recipe preparing step through the defect detection sensitivity determining step until the desired defect detection sensitivity is obtained while changing the tentative recipe parameter when the calculated defect detection ratio is lower than the desired defect detection ratio; and a recipe deciding step of deciding the recipe parameter at the time when the desired defect detection sensitivity is obtained, as a recipe parameter adaptive for the semiconductor defect inspection system.
According to the defect inspection recipe preparing method, the simulated defective wafer wherein a simulated defect data has been previously obtained is used, the detected defect data is compared with the simulated defect data to calculate the defect detection ratio based on the first provisional defect inspection recipe, so that it is possible to quantify the defect detection sensitivity of the first provisional defect inspection recipe. Moreover, it is possible to optimize recipe parameters by changing the tentative recipe parameters until the desired defection sensitivity. As a result, it is possible to prepare an appropriate defect inspection recipe independent of the level of skill of a person who prepares the recipe.
It is preferable that the above mentioned defect inspection recipe preparing method further comprises a second provisional recipe preparing step of preparing a second provisional defect inspection recipe using the decided recipe parameter; an actual inspection step of actually inspecting a defect of a semiconductor wafer as an object to be inspected using the second provisional defect inspection recipe;
an abnormality verification step of verifying whether the result of the defect inspection for the semiconductor wafer includes an abnormality; and a second provisional recipe modifying step of repeating the second provisional recipe preparing step through the abnormality verification step until the abnormality disappears while adjusting the decided recipe parameter, when the result of the defect inspection includes the abnormality.
Thus, the presence of abnormality in the results of the defect inspection for the semiconductor wafer serving as an object to be inspected is verified, and when there is an abnormality, the decided recipe parameters are adjusted until the abnormality disappears, so that it is possible to prepare a suitable defect inspection recipe.
It is advantageous that the defect inspection recipe preparing method further comprises a second provisional recipe preparing step of preparing a second provisional defect inspection recipe using the decided recipe parameter;
an actual inspection step of actually inspecting a defect of a semiconductor wafer as an object to be inspected using the second provisional recipe; an abnormality verification step of verifying whether the result of the defect inspection for the semiconductor wafer includes an abnormality; a step of determining the degree of the abnormality when the result of the detect inspection includes the abnormality; and, a final defect inspection recipe deciding step of classifying the determined degree of the abnormality to a first case where the determined degree of the abnormality is within a range in which the abnormality is removable by adjusting the second provisional defect inspection recipe and a second case where the determined degree of the abnormality is beyond the range in which the abnormality is removable by adjusting the second provisional defect inspection recipe and modifying the second provisional recipe in accordance with the result of the classification, wherein in the first case the second provisional recipe preparing step through the abnormality verification step are repeated while adjusting the decided recipe parameter until the abnormality disappears, and in the second case the first provisional recipe preparing step through the abnormality verification step are repeated while changing the tentative recipe parameter and the decided recipe parameter until the abnormality disappears.
Thus, when the degree of the abnormality is great, the tentative recipe parameters are set again at the first provisional recipe preparing step, so that it is possible to prepare the optimum defect inspection recipe.
The simulated defective wafer used in the defect inspection recipe preparing method may preferably the simulated defective wafer according to the present invention.
Thus, it is possible to choose the tentative recipe parameters in view of the kind of the defect layer arranged at the different vertical position from that of the simulated normal layer and/or the kind of a defect layer having a different shape from that of the simulated normal layer, so that it is possible to prepare a recipe file capable of carrying out a defect detection without omission.
In addition, the above mentioned recipe parameter may include the changeable focal length in the optical system or the electron optical system of the semiconductor defect inspection system, and it is preferable that the parameter setting step includes a step of setting the focal length corresponding to the defect kind which can exist at a predetermined position in directions perpendicular to the surface of the semiconductor wafer.
According to the prior art, when only a specific defect kind is inspected, a person who prepares a recipe presumes a focal length on the basis of his/her experience. Therefore, it is finally required that a data corresponding to a desired defect kind are extracted by a data processing, so that it takes a lot of time to carry out a data processing. According to the present invention, the feature of the defect kind and the defect detection sensitivity are thus quantified, so that an optimum recipe parameter for the desired defect kind can be chosen in a short time. Thus, there is provided a recipe file capable of greatly improving an inspection efficiency.